Field of the Invention
The present disclosure relates to an integrated circuit chip that includes circuitry producing a frequency-locked output without an off-chip input reference component, such as a crystal oscillator or other type of reference signal circuitry. The integrated circuit may include a frequency-locked voltage regulated loop including a voltage-controlled oscillator (VCO) that is regulated by a voltage regulator, which receives an internal accurate reference voltage and adjusts the VCO's output frequency to the locked frequency.
Description of Related Art
Phase-locked loops (PLLs) are widely used in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, or distribute precisely timed clock pulses in digital logic circuits such as microprocessors.
Referring to FIG. 1, a phase-locked loop (PLL) 100 is a closed-loop system that generates an output signal, fVCO, whose phase is related to the phase of an input frequency reference, fIN. Typically an off-chip stable crystal oscillator provides the stable input frequency reference, fIN. The phase-locked loop 100 includes a phase detector 102, a low pass filter 104, and a voltage-controlled oscillator (VCO) 108. The phase detector 102 compares two input frequencies, fIN and fVCO, and generates an output that is a measure of their phase difference. If fIN does not equal fVCO, the phase-error signal produced by the phase detector 102, after being filtered, is fed back to the VCO 110, causing the VCO frequency to change in the direction of fIN.
Referring to FIG. 2, a CMOS fully integrated frequency-locked loop (FLL) 200 includes a negative feedback circuit including two frequency-to-voltage converters (FVCs) 220, 222, a voltage controlled oscillator (VCO) 240, a high-gain operational amplifier 230, and two frequency dividers per M and per N, 210, 212. The feedback loop includes the divider per M 210, FVC2 220, operational amplifier 230, and VCO 240. Operationally, the frequency of the input reference signal (Fref), which is generated externally to the integrated frequency-locked loop 200, is divided by N and converted to a voltage (Vin1) by the FVC1 212. Similarly, the VCO oscillating frequency (Fosc) is divided by M and converted to a voltage (Vin2) by the FVC2 210. The high-gain operational amplifier 230 amplifies the difference between Vin1 and Vin2, and the resulting output voltage (Vctr) is employed to control the output frequency of the VCO 240. Since Vin1 and Vin2 correspond to Fref and Fosc, respectively, the FVC1 222 and FVC2 220 together with the operational amplifier 230 act as an analog frequency comparator. Depending on the voltage difference between Vin1 and Vin2, the operational amplifier output voltage Vctr will increase or decrease the VCO oscillating voltage frequency Fosc until the voltage Vin2 becomes equal to the voltage Vin1. At the time when Vin2 reaches Vin1, the output voltage Vctr ceases to vary and keeps the VCO 240 oscillating at a constant frequency. This integrated frequency-locked loop 200, however, requires an input reference frequency, Fref, that is generated externally.
There remains a need for an integrated circuit chip that includes a frequency-locked loop and does not require an off-chip reference component.